1. Field of the Invention
The present invention relates to a bank register circuit for holding data to be supplied to a multiply accumulate circuit (a device for carrying out a sum-of-products operation hereafter referred to as "MAC") of a microcomputer or a DSP (digital signal processor).
2. Description of the Prior Art
FIG. 1 shows a bank register circuit according to prior art.
The bank register circuit 100 consists of a bank register group 101 including bank registers MXA0 to MXAn and a bank register group 102 including bank registers MAA0 to MAAn. Data held in the bank register group 101 is supplied as input data to a sum-of-products unit 104 through an MX-bus 103. Data held in the bank register group 102 is supplied as coefficient data to the sum-of-products unit 104 through an MA-bus 105. The bank register groups 101 and 102 send and receive data to and from a system bus (M-bus) 106. The sum-of-products unit 104 provides an operation result to the bank register group 101 through a Z-bus 107, and the bank register group 101 holds the same.
FIG. 2A shows some of the bank registers incorporated in the bank register group 101. Each of the bank registers is composed of a write circuit 108, a flip-flop 109, a NOR gate 110, a read circuit 111, and an output circuit 112. The write circuit 108 selects data in one of the system bus 106 and Z-bus 107 and writes the selected data into the bank register. The flip-flop 109 fetches the selected data in synchronization with a write enable signal (one of WRX1 to WRXn) as shown in the timing chart of FIG. 3 and holds the data. The NOR gate 110 provides the NOR of the data held in the flip-flop 109 and a read enable signal (one of RDX1V to RDXnV). The read circuit 111 is an n-channel FET whose conductivity is controlled by the output of the NOR gate 110 and which is connected to the system bus 106, to provide the held data to the system bus 106 at the timing shown in FIG. 3. The output circuit 112 is a clocked inverter connected to the MX-bus 103 and provides the held data to the MX-bus 103 in response to an output enable signal (one of BX1 to BXn). The flip-flops 109 of the bank registers are cascaded to one another through clocked inverters 113.
FIG. 2B shows some of the bank registers incorporated in the bank register group 102. Each of the bank registers is composed of a flip-flop 114, a NOR gate 115, a read circuit 116, and an output circuit 117. The flip-flop 114 fetches data from the system bus 106 in synchronization with a write enable signal (one of WRA1 to WRAn) and holds the data. The NOR gate 115 provides the NOR of the data held in the flip-flop 114 and a read enable signal (one of RDA1V to RDAnV). The read circuit 116 is an n-channel FET whose conductivity is controlled by the output of the NOR gate 115 and which is connected to the system bus 106, to provide the held data to the system bus 106. The output circuit 117 is a clocked inverter whose conductivity is controlled by an output enable signal (one of A1 to An) and which provides the held data to the MA-bus 105.
According to this prior art, the system bus 106 receives large capacitance from the read circuits 111 and 116 connected thereto. This capacitance increases as the number of bank registers in the bank register groups 101 and 102, i.e., the number of read circuits 111 and 116 therein increases. Then, the read circuits 111 and 116 must have large driving capabilities. When the read circuits 111 and 116 are made of FETs as shown in FIG. 2, the FETs must be large. This results in increasing the size of the bank register circuit 100, the core size of the MAC, and the chip size of the system.
Large load capacitance on the system bus 106 slows down a speed of reading data from the bank registers for the system bus 106, to deteriorate a system operation frequency margin or a minimum operation source voltage margin.
In this way, the bank register circuit 100 of the prior art connects the read circuits 111 and 116 of the bank registers all in parallel to the system bus 106, to greatly increase load capacitance on the system bus 106. Each bank register having a read circuit (111 or 116) of large driving capability is unavoidably large to slow down a speed of reading data for the system bus 106.